Industrial Experience

Industrial R&D Projects worked in:

 Developer, Development of Random Test Program Generator (RTPG) for Texas Instruments TMS320C27x DSP in PERL, Texas Instruments Pvt. Ltd., Bangalore, 1998.

 Team member, Development Trace Data Export Peripheral Block for C27x-emulation chip (Ankur-E4), Texas Instruments Pvt. Ltd., Bangalore, 1998-1999.

 Team member, Development ISA-independent Scalable and Configurable Trace Data Export Receiver Chip (Drishti), Texas Instruments, Bangalore, 1999-2000.

 Team member, QuickTurn FPGA based Emulation of Trace Data Export Receiver Functional Netlist (Drishti), Texas Instruments Pvt. Ltd., Houston,Texas, U.S., 2000.

 Team member (short time involvement), Development of ISA of C28x, Texas Instruments, Bangalore, 2001.

 Team member (short time project), Development of C62x based DSL Modem (AJAX) chip, Texas Instruments, Bangalore, 2001.

 Team member (short time involvement), Development of Bi-Core (c62x DSP and MIPS) DSL Modem SoC (Sangam), Texas Instruments, Bangalore, 2001-2002.

Courses Taught/Teaching

I. VLSI Circuit Design (B.Tech., ECE,AU)

II. VLSI Circuits & Systems (M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU))

III. Analog Integrated Circuit Design (M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU))

IV. RFIC Design (M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU)).

V. Semiconductor Physics and Devices (B.Tech., ECE, AU and M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU))

VI. Memory Design (M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU))

VII. Information Theory and Coding (B.Tech., ECE, AU and M.Tech, School of VLSI Design, IIEST, Shibpur (formerly BESU))

VIII.FPGA Architecture (M.Tech., ECE, AU)

IX. Data Structure and Algorithms (M.Tech, PDSIT, IIEST, Shibpur (formerly BESU))

X. Communication Systems and Networking (M.Tech, PDSIT, IIEST, Shibpur (formerly BESU))

Research Area

 Electron Devices.

 Integrated Circuit Design

 Computer Architecture

 Finite Field Arithmetic Architectures.

 CNT based VLSI Interconnects.

Experience

Administrative Duties in Academics:

 Head (Officiating), Dept. of ECE, Aliah University from 13.07.2015 to 21.03.2016.

 Member of Examination Committee, Aliah University, for Three Academic Sessions 2013- 14, 2014-15 and 2015-16.

 Member Board of Studies, Dept. of ECE, Aliah University.

Conference Papers Published

1. Prasenjit Ray, Somsubhra Talapatra, and Hafizur Rahaman, “Low Latency LSB First Bit-Parallel Systolic Multiplier over GF(2m)”, in Progress in VLSI Design and Test (Ed. C. P. Ravikumar), Elite Publishing, New Delhi, pp.163-172, July 2008.

2. Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, and Santi P. Maity, " VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark," Progress in VLSI Design and Test (LNCS vol. 7373) (Eds. Sanatan Chattopadhyay et. al.), Springer Berlin Heidelberg, Berlin, pp. 375-376, July 2012.

3. Sudip Ghosh, Somsubhra Talapatra, Jayasree Sharma, Navonil Chatterjee, Hafizur Rahaman, and Santi P Maity, "Dual Mode VLSI Architecture for Spread Spectrum Image Watermarking using Binary Watermark," 2nd International Conference on Communication, Computing & Security (ICCCS-2012), Procedia Technology (Eds: Sanjay Kumar Jena and Banshidhar Majhi), Elsevier, vol. 6, pp. 784 – 791, October 2012.

4. Co-Author, “Challenges in the Design of a Scalable Data-Acquisition and Processing Systems-onSilicon,” ASP-DAC/VLSI Design 2002 ,pp: 781-788, 2002.

5. Somsubhra Talapatra, and Hafizur Rahaman, “Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m),” 13th EUROMICRO Conf. on Digital System Design (DSD-2010), France, September 2010.

6. Sudip Ghosh, Somsubhra Talapatra, Hafizur Rahaman, and Shanti P. Maity, “A Novel VLSI Architecture for Walsh-Hadamard Transform”, Asia Symposium on Quality Electronic Design (ASQED-2010), Malaysia, August 2010.

7. Somsubhra Talapatra, and Hafizur Rahaman, “Low Complexity Montgomery Multiplication Architecture for Elliptic Curve Cryptography over GF(pm)”, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC-2010), Spain, September 2010.

8. Sabir Ali Mondal, Somsubhra Talapatra, and Hafizur Rahaman, “Analysis, Modeling and Optimization of Transmission Gate Delay,” Asia Symposium on Quality Electronic Design (ASQED2011), Malaysia, July 2011.

9. Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, and Santi P Maity, International Conference on Advances in Computing and Communications (ICACC2012), August 2012.

10. Sudip Ghosh, Somsubhra Talapatra, Sudipta Chakraborty, Navonil Chatterjee, Hafizur Rahaman, and Santi P Maity, "VLSI Architecture for Spread Spectrum Image Watermarking in Walsh-Hadamard Transform Domain using Binary Watermark," Third International Conference on Computer and Communication Technology (ICCCT), November 2012.

11. Sudip Ghosh, Somsubhra Talapatra,Navonil Chatterjee, Nagakumar Reddy, Santi P Maity, and Hafizur Rahaman, "Multiplier-less VLSI Architecture of 1-D Hilbert Transform pair using Biorthogonal Wavelets," International Conference on Informatics, Electronics & Vision (ICIEV), May 2013.

12. Swagata Bhattacharya ; Somsubhra Talapatra, “A New Walsh Hadamard Transform Architecture Using Current Mode Circuit,” 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014.

Journal Papers Published

1. Somsubhra Talapatra, Hafizur Rahaman, and Jimson Mathew “Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m),” IEEE Trans. VLSI Syst., vol. 18(5), pp. 847- 852, May. 2010.

2. Sudip Ghosh, Somsubhra Talapatra, Navonil Chatterjee, Santi P Maity and Hafizur Rahaman, "FPGA based Implementation of Embedding and Decoding Architecture for Binary Watermark by Spread Spectrum Scheme in Spatial Domain," Bonfring International Journal of Advances in Image Processing, vol. 2, no. 4, pp. 1-8, December 2012.

Awards

i) Awarded “National Scholarship” in 1997 by Director of Public Instruction ,West Bengal.

ii) Awarded 1 st Prize in India region in “1997 TI-DSP Solution Challenge” by Dirctor,DSP Development,Texas Instruments Pvt. Ltd.

iii) Scholarship: GATE scholarship from 2003 to 2005.

Seminar/Conference/Workshop

I. “Challenges in VLSI Design: Cutting edge Perspective”, July 21-25, 2008 (TEQIP), Bengal Engineering & Science University, Shibpur, Howrah-711103, W.B., India.

II. “Advances in VLSI Signal Processing”, Dec 3-7, 2013, Dept. Of Electronics & Electrical Communication Engineering, IIT Kharagpur. 721302, W.B., India.

III. “Fundamentals & Applications of Nanomaterials (CU119)”, January 01-12, 2018, National Institute of Technical Teachers’ Training & Research (NITTTR), Salt Lake, Kolkata-700064, W.B., India.

Professional Society Activity

Journal Papers Reviewed:

I. One paper on Finite Filed Multiplier Architecture in IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Feb. 2014.

II. One paper on Finite Filed Multiplier Architecture in IEEE Transaction Very Large Scale Integration systems, Dec. 2014.

Other Notable Activities

Language : VHDL , System Verilog, C/C++.

Scripting Language: Perl.

Tool : Modelsim, Design compiler, IC compiler, Primetime, MATLAB, XST(Xilinx).

Verification language: Specman elite from verisity, System Verilog

RESUME   2018  

Academic and professional record can be found in the attached file.